K524G2GACB-A050

K524G2GACB-A050 General Description

GENERAL DESCRIPTION The K524G2GACB is a Multi Chip Package Memory which combines 4Gbit NAND Flash Memory an 2Gbit DDR synchronous high data rate Dynamic RAM. NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 250µs on the (1K+32)Word page and an erase operation can be performed in typical 2ms on a (64K+2K)Word block. Data in the data register can be read out at 42ns cycle time per Word. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the device′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The device is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility. In 2Gbit Mobile DDR, Synchronous design make a device controlled precisely with the use of system clock. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.FEATURES• Operating Temperature : -25°C ~ 85°C • Package : 137-ball FBGA Type - 10.5 x 13 x 1.2mmt, 0.8mm pitch • Voltage Supply : 1.7V ~ 1.95V • Organization - Memory Cell Array : (256M + 8M) x 16bit for 4Gb (512M + 16M) x 16bit for 8Gb DDP - Data Register : (1K + 32) x 16bit • Automatic Program and Erase - Page Program : (1K + 32)Word - Block Erase : (64K + 2K)Word • Page Read Operation - Page Size : (1K + 32)Word - Random Read : 40µs(Max.) - Serial Access : 42ns(Min.) • Fast Write Cycle Time - Page Program time : 250µs(Typ.) - Block Erase Time : 2ms(Typ.) • Command/Address/Data Multiplexed I/O Port • Hardware Data - Program/Erase Lockout During Power Transitions • Reliable CMOS Floating-Gate Technology -Endurance : 100K Program/Erase Cycles with 1bit/256Word ECC for x16 • Command Driven Operation • Unique ID for Copyright Protection • VDD/VDDQ = 1.8V/1.8V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • MRS cycle with address key programs - CAS Latency ( 3 ) - Burst Length ( 2, 4, 8, 16 ) - Burst Type (Sequential & Interleave) • EMRS cycle with address key programs - Partial Array Self Refresh ( Full, 1/2, 1/4 Array ) - Output Driver Strength Control ( Full, 1/2, 1/4, 1/8, 3/4, 3/8, 5/8, 7/8 ) • Internal Temperature Compensated Self Refresh • All inputs except data & DM are sampled at the positive going edge of the system clock(CK). • Data I/O transactions on both edges of data strobe, DM for masking. • Edge aligned data output, center aligned data input. • No DLL; CK to DQS is not synchronized. • DM0 - DM3 for write masking only. • Auto refresh duty cycle - 7.8us • Clock stop capability

Features

• Operating Temperature : -25°C ~ 85°C
• Package : 137-ball FBGA Type - 10.5 x 13 x 1.2mmt, 0.8mm pitch

Specifications