Xilinx AM29LV400

AM29LV400 General Description

GENERAL DESCRIPTIONThe Am29LV400 is a 4 Mbit, 3.0 volt-only Flash memory organized as 524,288 bytes or 262,144 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system using only a single 3.0 volt VCC supply. No VPP is required for write or erase operations. The device can also be programmed in standard EPROM programmers.DISTINCTIVE CHARACTERISTICS■ Single power supply operation    — Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications    — Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors■ High performance    — Full voltage range: access times as fast as 100 ns    — Regulated voltage range: access times as fast as 90 ns■ Ultra low power consumption (typical values at 5 MHz)    — 200 nA Automatic Sleep mode current    — 200 nA standby mode current    — 10 mA read current    — 20 mA program/erase current■ Flexible sector architecture    — One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and seven 64 Kbyte sectors (byte mode)    — One 8 Kword, two 4 Kword, one 16 Kword, and seven 32 Kword sectors (word mode)    — Supports full chip erase    — Sector Protection features:        A hardware method of locking a sector to prevent any program or erase operations within that sector        Sectors can be locked via programming equipment        Temporary Sector Unprotect feature allows code changes in previously locked sectors■ Top or bottom boot block configurations available■ Embedded Algorithms    — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors    — Embedded Program algorithm automatically writes and verifies data at specified addresses■ Typical 1,000,000 write cycles per sector (100,000 cycles minimum guaranteed)■ Package option    — 48-ball FBGA    — 48-pin TSOP    — 44-pin SO■ Compatibility with JEDEC standards    — Pinout and software compatible with singlepower supply Flash    — Superior inadvertent write protection■ Data# Polling and toggle bits    — Provides a software method of detecting program or erase operation completion■ Ready/Busy# pin (RY/BY#)    — Provides a hardware method of detecting program or erase cycle completion■ Erase Suspend/Erase Resume    — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation■ Hardware reset pin (RESET#)    — Hardware method to reset the device to reading array data

Features

• Single power supply operation
• — Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications
• — Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors
• High performance
• — Full voltage range: access times as fast as 100 ns
• — Regulated voltage range: access times as fast as 90 ns
• Ultra low power consumption (typical values at 5 MHz)
• — 200 nA Automatic Sleep mode current
• — 200 nA standby mode current
• — 10 mA read current
• — 20 mA program/erase current
• Flexible sector architecture
• — One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and seven 64 Kbyte sectors (byte mode)
• — One 8 Kword, two 4 Kword, one 16 Kword, and seven 32 Kword sectors (word mode)
• — Supports full chip erase
• — Sector Protection features:
• A hardware method of locking a sector to prevent any program or erase operations within that sector
• Sectors can be locked via programming equipment
• Temporary Sector Unprotect feature allows code changes in previously locked sectors
• Top or bottom boot block configurations available
• Embedded Algorithms
• — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors
• — Embedded Program algorithm automatically writes and verifies data at specified addresses
• Typical 1,000,000 write cycles per sector (100,000 cycles minimum guaranteed)
• Package option
• — 48-ball FBGA
• — 48-pin TSOP
• — 44-pin SO
• Compatibility with JEDEC standards
• — Pinout and software compatible with singlepower supply Flash
• — Superior inadvertent write protection
• Data# Polling and toggle bits
• — Provides a software method of detecting program or erase operation completion
• Ready/Busy# pin (RY/BY#)
• — Provides a hardware method of detecting program or erase cycle completion
• Erase Suspend/Erase Resume
• — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation
• Hardware reset pin (RESET#)
• — Hardware method to reset the device to reading array data