Microchip KSZ8765CLXIC

KSZ8765CLXIC General Description

The KSZ8765 is a highly integrated, Layer 2-managed, five-port switch with numerous features designed to reduce overall system cost. It is intended for cost-sensitive applications requiring four 10/100Mbps copper ports and one 10/100/1000Mbps Gigabit uplink port.

The KSZ8765CLX incorporates a small package outline, low power consumption with internal biasing, and on-chip termination. Its extensive set of features include enhanced power management, programmable rate limiting and priority ratio, tagged and port-based VLAN, port-based security and ACL rule-based packet filtering technology, QoS priority with four queues, management interfaces, enhanced MIB counters, high-performance memory bandwidth, and a shared memory-based switch fabric with non-blocking support.

The KSZ8765CLX provides support for multiple CPU data interfaces to effectively address both current and emerging fast Ethernet and Gigabit Ethernet applications where the Port 5 GMAC can be configured to any of the GMII, RGMII, MII, and RMII modes.The KSZ8765CLX is built upon Microchip's industry-leading Ethernet analog and digital technology, with features designed to offload host processing and streamline the overall design.

- Two integrated MAC/PHYs 100Base-FX on Port 1 and Port 2
- Two integrated MAC/PHYs 10/100Base-T/TX on Port 3 and Port 4
- One integrated 10/100/1000Base-T/TX GMAC with selectable GMII, RGMII, MII, and RMII interfaces
- Small 80-pin LQFP package

A robust assortment of power management features including energy-efficient Ethernet (EEE), power management event (PME), and wake-on-LAN (WoL) have been designed in to satisfy energy efficient environments.All registers in the MAC/PHY units can be managed through the SPI interface. MIIM PHY registers can be accessed through the MDC/MDIO interface.

Microchip's complimentary and confidential LANCheck® online design review service is available for customers who have selected our products for their application design-in. The LANCheck online design review service is subject to Microchip's Program Terms and Conditions and requires a myMicrochip account.

Features

• Integrated 5-port 10/100 Layer-2 switch with Gigabit uplink
• New generation switch with four MACs, one GMAC (for uplink) and four PHYs (two 10/100Base-T/TX & two 100Base-FX) that are fully compliant with the IEEE 802.3u standard
• 10/100Base-T/TX & 100Base-FX switch system which combines a switch engine, frame buffer management, address lookup table, queue management, MIB counters, MAC, and PHY transceivers
• Rapid spanning tree support (RSTP) for topology management
• Microchip LinkMD® cable diagnostic capabilities for determining cable opens, shorts, and length
• Advanced Switch Capabilities
• IEEE 802.1q VLAN support for up to 128 active VLAN groups (full range 4096 of VLAN IDs)
• Support 802.1x port-based security and MAC-based authentication via access control lists (ACL)
• QoS/CoS Packet Prioritization Support
• 802.1p, DiffServ-based and Re-mapping of 802.1p priority field, per-port basis on four priority levels
• 4 priority queues with dynamic mapping for IEEE 802.1P, IPV4 ToS (DiffServ), IPV6 Traffic Class, etc
• Programmable rate limiting at the ingress and egress ports on a per port basis
• Comprehensive Configuration Register Access
• High-speed SPI (4-wire, up to 50MHz) interface to access all internal registers
• MII management (MIIM, MDC/MDIO 2 wire) interface to access all PHY registers per IEEE 802.3 specification
• Control registers configurable on-the-fly
• Switch Monitoring Features
• Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or MII/RMII
• MIB counters for fully-compliant statistics gathering (36 MIB counters per port)
• Low Power Dissipation
• Full-chip software power-down
• Energy detect power-down (EDPD)
• Support IEEE P802.3az Energy Efficient Ethernet (EEE)
• Wake on LAN (WoL) support

Specifications