ST STM32F303ZET6

STM32F303ZET6 General Description

The STM32F303xD/E family is based on the high-performance ARM®Cortex®-M4 32-bit RISC core with FPU operating at a frequency of 72 MHz, and embedding a floating point unit (FPU), a memory protection unit (MPU) and an embedded trace macrocell (ETM). The family incorporates high-speed embedded memories (512-Kbyte Flash memory, 80-Kbyte SRAM), a flexible memory controller (FSMC) for static memories (SRAM, PSRAM, NOR and NAND), and an extensive range of enhanced I/Os and peripherals connected to an AHB and two APB buses.The devices offer four fast 12-bit ADCs (5 Msps), seven comparators, four operational amplifiers, two DAC channels, a low-power RTC, up to five general-purpose 16-bit timers, one general-purpose 32-bit timer, and up,to three timers dedicated to motor control. They also feature standard and advanced communication interfaces: up to three I2Cs, up to four SPIs (two SPIs are with multiplexed full-duplex I2Ss), three USARTs, up to two UARTs, CAN and USB. To achieve audio class accuracy, the I2S peripherals can be clocked via an external PLL.The STM32F303xD/E family operates in the -40 to +85°C and -40 to +105°C temperature ranges from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications.The STM32F303xD/E family offers devices in different packages ranging from 64 to 144 pins.Depending on the device chosen, different sets of peripherals are included.STM32 Nucleo-32 development board with STM32F303.STM32 Nucleo-64 development board with STM32F303.Evaluation board with STM32F303VE MCU.Discovery kit with STM32F303VC MCU.ST-LINK/V2 in-circuit debugger/programmer for ST.STM32 Nucleo-144 development board with STM32F30.

Features

• Core: ARM^®Cortex^®-M4 32-bit CPU with 72 MHz FPU, single-cycle multiplication and HW division, 90 DMIPS (from CCM), DSP instruction and MPU (memory protection unit)
• Operating conditions:
  • V_DD, V_DDAvoltage range: 2.0 V to 3.6 V
• Memories
  • Up to 512 Kbytes of Flash memory
  • 64 Kbytes of SRAM, with HW parity check implemented on the first 32 Kbytes.
  • Routine booster: 16 Kbytes of SRAM on instruction and data bus, with HW parity check (CCM)
  • Flexible memory controller (FSMC) for static memories, with four Chip Select
• CRC calculation unit
• Reset and supply management
  • Power-on/Power-down reset (POR/PDR)
  • Programmable voltage detector (PVD)
  • Low-power modes: Sleep, Stop and Standby
  • V_BATsupply for RTC and backup registers
• Clock management
  • 4 to 32 MHz crystal oscillator
  • 32 kHz oscillator for RTC with calibration
  • Internal 8 MHz RC with x 16 PLL option
  • Internal 40 kHz oscillator
• Up to 115 fast I/Os
  • All mappable on external interrupt vectors
  • Several 5 V-tolerant
• Interconnect matrix
• 12-channel DMA controller
• Four ADCs 0.20 μs (up to 40 channels) with selectable resolution of 12/10/8/6 bits, 0 to 3.6 V conversion range, separate analog supply from 2.0 to 3.6 V
• Two 12-bit DAC channels with analog supply from 2.4 to 3.6 V
• Seven ultra-fast rail-to-rail analog comparators with analog supply from 2.0 to 3.6 V
• Four operational amplifiers that can be used in PGA mode, all terminals accessible with analog supply from 2.4 to 3.6 V
• Up to 24 capacitive sensing channels supporting touchkey, linear and rotary touch sensors
• Up to 14 timers:
  • One 32-bit timer and two 16-bit timers with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input<

Specifications