KSZ9897STXI-TR

KSZ9897STXI-TR General Description

The KSZ9897 is a fully integrated layer 2, managed,seven-port gigabit Ethernet switch with numerousadvanced features. Five of the seven ports incorporate10/100/1000 Mbps PHYs. The other two ports haveinterfaces that can be configured as SGMII, RGMII, MII or RMII.Either of these may connect directly to a host processor orto an external PHY.

Full register access is available by SPI or I²C interfaces,and by optional in-band management via any of the data ports.PHY register access is provided by a MIIM interface.

Security features include support for IEEE 802.1X port-based authentication and Access Control List (ACL) filtering.

An assortment of power-management features includingEnergy-Efficient Ethernet (EEE) have been designed in tosatisfy energy efficient environments.

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Features

• Non-blocking wire-speed Ethernet switching fabric
• Full-featured forwarding and filtering control, including Access Control List (ACL) filtering
• IEEE802.1X support (Port-Based Network Access Control)
• IEEE802.1Q VLAN supportfor 128 active VLAN groups and the full range of 4096 VLAN IDs
• IEEE802.1p/Q tag insertion or removal on a per port basis and support for double-tagging
• VLAN ID tag/untag options on per port basis
• IEEE802.3x full-duplex flow control and half-duplex back pressure collision control
• IGMPv1/v2/v3 snooping for multicast packet filtering
• IPv6 multicast listener discovery (MLD) snooping
• QoS/CoS packets prioritization support: 802.1p, DiffServ-based and re-mapping of 802.1p priority field per-port basis on four priority levels
• IPv4/IPv6 QoS support
• Programmable rate limiting at ingress and egress ports
• Broadcast storm protection
• Four priority queues with dynamic packet mapping for IEEE802.1p, IPv4 DIFFSERV, IPv6 TrafficClass
• MAC filtering function to filter or forward unknown unicast, multicast and VLAN packets
• Self-address filtering for implementing ring topologies
• High-speed SPI (4-wire, up to 50MHz) interface to access all internal registers
• I2C Interface to access all registers
• MII management (MIIM, MDC/MDIO 2 wire) interface to access all PHY registers per IEEE 802.3 specification
• In-band management to access all registers via any of the seven ports, strap enabled
• I/O pin strapping facility to set certain register bits from I/O pins at reset time
• Control registers configurable on-the-fly
• Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or MII/RMII
• MIB counters for fully-compliant statistics gathering (34 MIB counters per port)
• Full-chip software power-down
• Energy detect power-down (EDPD)
• Wake on LAN (WoL) support

Specifications