Microchip KSZ9131MNXC

KSZ9131MNXC General Description

The KSZ9131 is a completely integrated triple-speed (10Base-T/100Base-TX/1000Base-T) Ethernet physical-layer transceiver for transmission and reception of data on standard CAT-5, CAT-5e and CAT6 unshielded twisted pair (UTP) cable.

The KSZ9131RNX provides Reduced Gigabit Media Independent Interface RGMII and the KSZ9131MNX offers the industry-standard GMII/MII (Gigabit Media Independent Interface/Media Independent Interface) for connection to GMII/MII MACs in Gigabit Ethernet processors and switches for data transfer at 1000Mbps or 10/100Mbps.

The KSZ9131 reduces board cost and simplifies board layout by using on-chip termination resistors for the four differential pairs and by integrating an LDO controller to drive a low-cost MOSFET to supply the 1.2V core.

The KSZ9131 offers diagnostic features to facilitate system bring-up and debugging in production testing and in product deployment. Parametric NAND tree support enables fault detection between KSZ9131 I/Os and the board. The LinkMD® TDR-based cable diagnostic identifies faulty copper cabling. Remote and local loopback functions verify analog and digital data paths.

The standard KSZ9131RNX is available in the 48-pin, RoHS compliant QFN package, and the AEC-Q100 automotive qualified parts, KSZ9131RNXU and KSZ9131RNXV, are available in the 48-pin lead-RoHS compliant VQFN (wettable) package. The KSZ9131MNX is available in a 64-pin, RoHS Compliant QFN package.

Microchip's complimentary and confidential LANCheck® online design review service is available for customers who have selected our products for their application design-in. The LANCheck online design review service is subject to Microchip's Program Terms and Conditions and requires a myMicrochip account.

Features

• Single-chip 10/100/1000Mbps IEEE 802.3 compliant Ethernet transceiver
• GMII/MII/RGMII with 3.3V/2.5V/1.8V tolerant I/Os
• Auto-negotiation to automatically select the highest linkup speed (10/100/1000Mbps) and duplex (half/full)
• On-chip termination resistors for the differential pairs
• On-chip LDO controller to support single 3.3V supply operation – requires only one external FET to generate 1.2V for the core
• Jumbo frame support up to 16KB
• 125MHz Reference Clock Output
• Energy-detect power-down mode for reduced power consumption when the cable is not attached
• Wake-on-LAN (WOL) support with robust custom-packet detection
• Programmable LED outputs for link, activity, and speed
• Baseline wander correction
• LinkMD® TDR-based cable diagnostic to identify faulty copper cabling
• Parametric NAND tree support to detect faults between chip I/Os and board
• Loopback modes for diagnostics
• Automatic MDI/MDI-X crossover to detect and correct pair swap at all speeds of operation
• MDC/MDIO management interface for PHY register configuration
• Automatic detection and correction of pair swaps, pair skew, and pair polarity
• Interrupt pin option
• Power-down and power-saving modes
• Operating voltages: Core (DVDDL, AVDDL, AVDDL_PLL): 1.2V (external FET or regulator) VDD I/O (DVDDH): 3.3V, 2.5V, or 1.8V Transceiver (AVDDH): 3.3V or 2.5V (commercial temp)
• Core (DVDDL, AVDDL, AVDDL_PLL): 1.2V (external FET or regulator)
• VDD I/O (DVDDH): 3.3V, 2.5V, or 1.8V
• Transceiver (AVDDH): 3.3V or 2.5V (commercial temp)
• Available in 48-pin QFN (7mm x 7mm) and 64-pin QFN (8mm x 8mm) packages

Specifications